Description

The 2x QSFP28 FMC is an FPGA Mezzanine Card designed to connect up to two QSFP28 modules to your FPGA or MPSoC development board. It includes a jitter-attenuating clock multiplier, the Skyworks Si5328, which generates two precision clocks programmable from 8kHz to 808MHz. Additionally, the card supports the use of a recovered clock for Synchronous Ethernet applications. For more detailed information on the 2x QSFP28 FMC, including datasheets, schematics and example designs, please see the datasheet.

• 2x QSFP28 slots compatible with QSFP, QSFP+ and QSFP28 modules
• Jitter-attenuating clock multiplier (Skyworks Si5328) with support for recovered clock and SyncE applications
• HPC FMC compliant with VITA 57.1
• Supports a wide range of I/O voltages (VADJ): 1.2V-3.3V
• Reference designs for multiple FPGA and MPSoC development boards
• Straightforward tech support

Intended use and compliance

The 2x QSFP28 FMC is an FPGA Mezzanine Card, a sub-assembly intended for incorporation into apparatus by professional integrators. It has no standalone function: it operates only when mounted on a compatible FMC carrier and driven by an FPGA design created by the integrator. Opsero has assessed the card's electromagnetic compatibility under the reference conditions described in its EMC integration notes and declares conformity on that basis. The integrator is responsible for the conformity of the apparatus into which the card is incorporated, including its enclosure, cabling, power supply and firmware. This is Class A equipment: in a residential environment it may cause radio interference, in which case the user may be required to take adequate measures.

Declarations and supporting information: Product compliance. EMC integration notes.

Frequently asked questions

What FPGA I/O voltages (VADJ) are supported by 2x QSFP28 FMC?

The 2x QSFP28 FMC was designed with level translators to enable it to support any VADJ voltage in the range of 1.2VDC to 3.3VDC.

Is the 2x QSFP28 FMC compatible with my FPGA board?

In general terms, the FPGA development board needs to have gigabit transceivers to use the 2x QSFP28 FMC, and those transceivers must be connected to the DP0-3 pins of the FMC connector. It also needs to be able to supply a VADJ voltage between 1.2VDC to 3.3VDC. Please visit the product website for a list of compatible FPGA boards and detailed compatibility requirements.

Do I need any purchased IP to use the 2x QSFP28 FMC?

No, not for 100G Ethernet. Our example designs for the 2x QSFP28 FMC use the hardened 100G Ethernet MACs that are built into many AMD devices: the MRMAC in Versal devices, and the CMAC in Zynq UltraScale+ RFSoC and Kintex UltraScale+ devices. These hard MACs require a license key from AMD, but it is free of charge.

• 100G/40G Ethernet: 100G Ethernet over the MRMAC or CMAC, with the packet data moved to and from DDR by DMA and handled by the processor. On boards with GTH transceivers (such as the ZCU102 and ZCU106) the ports run at 40G using the AMD 40G/50G Ethernet Subsystem, which is a paid IP core (an evaluation license is available from AMD).
• Zircon IP stack (free): Puts the open-source Zircon IP stack from the Taxi transport library behind the MRMAC or CMAC, for full line-rate UDP processing in hardware. The Taxi library is licensed under the CERN-OHL-S-2.0 (a reciprocal open hardware license) or under a commercial license from FPGA Ninja, so please review its terms before shipping a product built on it.